1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate electrode structures including a high-k gate dielectric.
2. Description of the Related Art
Advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, include a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, has been a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely thin gate dielectric may be restricted to high speed signal paths, whereas transistor elements with a thicker gate dielectric may be used for less critical circuit portions, such as storage transistor elements and the like, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for many types of circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
As is well known, the work function of the gate dielectric material may significantly affect the finally obtained threshold voltage of field effect transistors, in particular when the doping in the channel region is reduced, which is presently accomplished by appropriately doping the polysilicon material, which may be used in combination with a silicon oxide-based material in conventional gate electrode structures. Upon introducing a high-k dielectric material, the adjustment of an appropriate work function may require the incorporation of appropriate metal species into the gate dielectric material, for instance in the form of lanthanum, aluminum and the like, in order to obtain appropriate work functions and thus threshold voltages for P-channel transistors and N-channel transistors. Moreover, the sensitive high-k dielectric material may have to be protected during the processing, while also a contact with well-established materials, such as silicon and the like, may be considered disadvantageous since the Fermi level may be significantly affected upon contacting a high-k dielectric material, such as hafnium oxide, with a polysilicon material. Consequently, a metal-containing cap material may typically be provided on the high-k dielectric material when provided in an early manufacturing stage. Additionally, the metal-containing material may provide superior conductivity and may also avoid any depletion zone, which may be observed in polysilicon gate electrode structures. Consequently, a plurality of additional process steps and material systems are introduced in well-established CMOS process techniques in order to form gate electrode structures including a high-k dielectric material in combination with a metal-containing electrode material. In other strategies, replacement gate approaches may be applied in which essentially gate electrode structures may be provided as placeholder material systems, wherein, after finishing the basic transistor configurations, the gate electrode structures may be replaced by at least an appropriate metal-containing electrode material, possibly in combination with a high-k dielectric material, thereby requiring complex process sequences for removing the initial gate material, such as polysilicon, and forming appropriate metal species, wherein appropriate work function values also have to be adjusted by incorporating corresponding work function adjusting species, as discussed above.
In addition to enhancing performance of gate electrode structures by incorporating a high-k dielectric material in sophisticated semiconductor devices, frequently, transistor elements of different characteristics, for instance of different leakage behavior, different threshold voltage, and the like, have to be provided, thereby requiring a gate dielectric material of different material composition and/or of different thickness and/or different work function values.
In sophisticated technologies based on high-k metal gate electrode structures, the per se extremely complex patterning process for forming gate electrode structures of the desired reduced gate length may become additionally more complex in so-called “gate first” approaches in which the different transistor characteristics, such as different threshold voltages, have to be adjusted in an early manufacturing stage. That is, in some approaches, the gate layer stacks of transistors of different conductivity type may comprise very different material layers and barrier layers, which may thus contribute to an increased degree of complexity during the patterning process, which in turn may result in patterning-related irregularities. Upon introducing further differences in the gate layer stack, for instance by requiring different threshold voltage levels for otherwise similar transistors, the complexity of the patterning process may be even further increased, thereby making these approaches less than desirable in volume production environments.
In other approaches, very similar gate layer stacks for P-channel transistors and N-channel transistors may be provided, while nevertheless enabling the adjustment of appropriate work function values with respect to the semiconductor material of these transistor elements. Although these approaches may allow the patterning of gate electrode structures of P-channel transistors and N-channel transistors with superior integrity compared to other approaches using very different gate layer stacks, the adjustment of different threshold voltages for a plurality of semiconductor devices, such as transistors of the same conductivity type with different transistor behavior, may still be difficult, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101 and a semiconductor layer 102 formed above the substrate 101. The semiconductor layer 102 is typically provided in the form of a silicon material, as explained above. Furthermore, a first semiconductor region or active region 102A and a second semiconductor region or active region 102B are provided in the semiconductor layer 102. The active regions 102A, 102B are to be understood as semiconductor regions in and above which transistor elements are to be formed on the basis of gate electrode structures including a high-k dielectric material. In the example shown, it may be assumed that an N-channel transistor is to be formed in and above the active region 102A, while a P-channel transistor is to be formed in and above the active region 102B. Furthermore, in the manufacturing stage shown, a layer stack 110 is formed above the active regions 102A, 102B and comprises a gate dielectric material including a first dielectric material 111, such as a silicon dioxide material, a silicon oxynitride material and the like, in combination with a high-k dielectric material 112, such as a hafnium oxide-based material and the like. Furthermore, the layer stack 110 comprises a diffusion layer 113A which may represent any appropriate material layer including a metal species for adjusting the work function of a gate electrode structure to be formed on the active region 102A. For instance, the layer 113A may comprise lanthanum which, when diffused into the underlying material, may result in a desired work function in combination with an electrode material still to be formed. On the other hand, the layer stack 110 may comprise a diffusion layer 113B formed above the active region 102B and comprising an appropriate metal species, such as aluminum, which may result in a desired work function in combination with the electrode metal still to be formed. Furthermore, in the example shown, a further cap layer 114, such as a titanium nitride material, may be provided so as to confine the materials 113A, 113B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of any well-established process techniques including processes for forming an isolation structure (not shown) in order to define the lateral size and position of the active regions 102A, 102B within the semiconductor layer 102. Prior to or after forming the isolation structures, an appropriate well dopant species may be incorporated, thereby defining the basic conductivity of the transistor elements still to be formed in and above the active regions 102A, 102B. It should be appreciated that other dopant species may also be incorporated in order to control the resulting threshold voltage, wherein, however, in advanced semiconductor devices, typically, the dopant concentration in the channel regions of these devices may have to be reduced in order to reduce leakage currents and reduce charge carrier scattering. Consequently, upon providing a reduced channel doping, the resulting threshold voltage may be substantially determined on the basis of the electronic characteristics of the semiconductor material and the work function of the gate electrode material in combination with the intermediate gate dielectric materials 111 and 112. Next, the gate dielectric material 111 may be formed, for instance, by deposition, oxidation and the like, depending on the overall process strategy. Thereafter, the high-k dielectric material 112 is deposited, for instance, by chemical vapor deposition (CVD) and the like. For example, the thickness of the material layer 111 may be one nanometer and less, while the layer 112 having the increased dielectric constant may have a thickness of one nanometer to several nanometers, depending on the desired level of leakage currents and the like. Thereafter, the layers 113A, 113B may be formed, for instance, by depositing the layer 113A and removing the material from above the active region 102B. Thereafter, the layer 113B may be deposited and may be removed from above the active region 102A on the basis of appropriate etch masks and etch recipes. Finally, the titanium nitride material 114 may be deposited on the basis of sputter deposition and the like. It should be appreciated that other process strategies may be applied, for instance by forming an additional barrier material, for instance after removing one of the layers 113A, 113B from above one of the active regions 102A, 102B and depositing the other one of the layers 113A, 113B without requiring the removal of an unwanted portion of this material layer. Thereafter, a heat treatment 103, for instance applying temperatures several hundred degrees Celsius to nine hundred degrees Celsius may be applied in order to initiate a diffusion of the metal species in the layers 113A, 113B into the high-k dielectric material 112, thereby also positioning the metal species at an interface formed by the layers 111 and 112. As will be discussed later on with reference to FIG. 1c, it is assumed that the incorporated metal species may build up dipole charges, which in turn may result in a corresponding adaptation of the work function after forming a gate electrode material.
After the anneal process 103, the layers 114 and 113A, 113B may be removed, for instance, by wet chemical etch recipes, wherein the high-k dielectric material 112 may act as an efficient etch stop material. Next, a metal-containing electrode material, such as titanium nitride or any other appropriate electrode metal, may be deposited in combination with a conventional electrode material, such as silicon, which may be accomplished on the basis of well-established process techniques. Consequently, the same electrode layer stack may be provided above the active regions 102A, 102B. Moreover, additional materials, such as dielectric cap materials, hard mask materials and the like, may be applied as are required for the patterning of the resulting layer stack.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a gate electrode structure 110A is formed on the active region 102A and a gate electrode structure 110B is formed on the active region 102B. The gate electrode structure 110A comprises the gate dielectric materials 111 and 112 in which, due to the preceding treatment, the work function metal species 113A, such as lanthanum, may be incorporated. Similarly, the gate electrode structure 110B comprises the gate dielectric materials 111 and 112 having incorporated therein the work function metal species 113B, such as aluminum. Moreover, the gate electrode structures 110A, 110B comprise metal-containing electrode material 115, such as titanium nitride, followed by a further electrode material 116, such as silicon. Furthermore, a dielectric cap material 117, for instance in the form of silicon nitride, silicon dioxide and the like, is typically provided. Consequently, the gate electrode structures 110A, 110B may have basically the same configuration, which may represent a significant advantage upon patterning the various material layers formed therein. Consequently, an appropriate etch strategy may be applied for both gate electrode structures 110A, 110B, thereby obtaining a highly uniform process result, thereby making this approach superior compared to other approaches in which significantly different gate electrode layer stacks may have to be patterned. On the other hand, despite the same electrode materials provided in the gate electrode structures 110A, 110B, a desired threshold voltage may be obtained for the active regions 102A, 102B due to the presence of the different work function adjusting species 113A, 113B.
FIG. 1c schematically illustrates the electronic situation of the gate electrode structure 110A according to a band model. It should be appreciated that the present application is not to be restricted to any theory disclosed herein, which may nevertheless be helpful in understanding the basic mechanism for adjusting the threshold voltages of transistors. For example, as illustrated, the dielectric gate materials 111 and 112 may separate the channel region, indicated as 102A, representing a part of the active region 102A as shown at the right hand side, from the gate electrode material 115 illustrated at the left hand side of the dielectric materials 111 and 112. Furthermore, due to the previously incorporated work function metal species 113A, deep hole charges 113D may be generated, in particular at an interface between the materials 111 and 112. Consequently, the energy levels of the lower conduction band edge indicated as EC and the upper edge of the valence band, indicated as EV, may be appropriately bent at the interface of the layer 111 and the channel region 102A, which is strongly influenced by the charges 113D. Consequently, for a given work function of the material 115, an appropriate adaptation with respect to the flat band energy, indicated as EF, may be accomplished for both types of gate electrode structures since a corresponding adaptation may also be accomplished for the active region 102B (FIG. 1b) on the basis of the work function metal species 113B. Hence, the appropriate threshold voltage for both types of transistors may be obtained, irrespective of the fact that the actual electrode material may be the same for both gate electrode structures 110A, 110B of FIG. 1b. 
Although the concept of providing diffusion cap materials is promising, i.e., the layers 113A, 113B, possibly in combination with the material 114 (FIG. 1a) in an early manufacturing stage for adjusting the work function and thus threshold voltage for a common electrode material for both types of transistors, it is difficult to provide transistor elements of different threshold voltage, which may typically be required in complex integrated circuits when, for instance, different “flavors” of basically the same transistor configuration may be required, or in mixed signal applications using analog and digital circuit portions.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.